Design for Test Engineer (Temporary Contract Staff Augmentation Role)
Role summary
Ampere is seeking a temporary Design for Test (DFT) Engineer for a 6-month contract role. This CAD engineering position involves working with global teams and EDA vendors to develop DFT flows using Spyglass and Silicon Insight tools. Responsibilities include RTL scan DRC analysis, scan coverage estimation, pattern generation, test bringup, debug, and silicon characterization for complex products. The role requires expertise in various DFT architectures, scripting, and industry-standard tools.
Description
Invent the future with us.
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing.
By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow.
Ampere is seeking to fill a temporary staff augmentation CAD Engineering role supporting our DFT Team for an anticipated period of 6 months with a possibility of extension.
Scope Of Work
The ideal candidate is a CAD engineer who will work with DFT and multi-functional global teams, EDA vendors to develop Spyglass based DFT (TestMax) scan DRC analysis scan coverage estimation flows in the RTL, developing SiliconInsight based pattern generation, test bringup, debug and silicon characterization flows for our next generation complex products.
Education, Skills, & Experience Desired
- Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- 10 years of related experience
- Expert-level proficiency with Spyglass DFT for various DFT DRC checks and deep understanding of its rule sets
- Extensive hands-on experience with Mentor Tessent, particularly Tessent MBIST for memory BIST insertion, verification, and pattern generation
- Strong familiarity with Silicon Insight tools to perform silicon debug and diagnostic platforms for failure analysis and yield improvement
- Deep understanding of DFT architectures, including Scan, JTAG, Boundary Scan, ATPG, and MBIST
- Proficiency in Verilog/VHDL for RTL design and understanding
- Strong scripting skills (Python, Tcl) for automation and flow development
- Experience in scan insertion flows
- Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features
- Experience with industry standard simulation tools and Verdi for debug
- Experience in revision control systems like GIT, perforce etc.
- Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage
- Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion
Engagement Arrangements
As a Contingent Worker, you will work as an employee of a Staffing Vendor firm, who provides staff augmentation and payroll services for Ampere Computing. The staffing firm offers weekly pay based on approved timecard submittal, medical benefits, and other employment benefits, based on eligibility. The hourly pay range for this role is between $96.53 and $140.38 per hour.
The role is based at Ampere’s Santa Clara, CA office. This role is full-time onsite.
Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.