Principal Digital Design Engineer

San Jose, California, United StatesFull TimePrincipalPosted 19 days agoVisa sponsorship available

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Role summary

The Principal Digital Design Engineer will join the DSP SerDes team to develop advanced high-speed SerDes wireline and optical transceivers for AI systems. This role requires 5-10 years of experience in digital design for high-speed DSP data paths, proficiency in System Verilog, and experience with EDA tools for synthesis, lint, CDC, and Prime Time. The engineer will be responsible for critical design blocks throughout the full design cycle, from micro-architecture to tapeout, including timing fixes, area/power optimizations, and silicon issue resolution. Collaboration with DSP Architecture, PD, and DV teams is essential for feature definition, optimization, and bug fixing.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description: As a Digital Designer in the DSP SerDes team, you will join a pivotal project to develop advanced high speed SerDes wireline and optical transceivers for AI systems.

Basic Qualifications:

Hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

5-10 years of experience in digital design for high-speed DSP data path.

Be proficient in coding System Verilog for complex design blocks.

Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time.

Have experience taking design blocks through the full design cycle, from micro-architecture to tapeout.

Have experience with timing fixes, area and power optimizations, and resolving silicon issues.

Required Experience:

Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery.

Code and deliver high-quality RTL to the PD and DV teams.

Collaborate with the DSP Architecture team to define new features and suggest optimizations for power, latency, and performance.

Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations.

Partner with the DV team to root-cause and fix design bugs.

Preferred Experience:

Experience in digital design for high speed data path in 100G+ PAM4 DSP SerDes

Experience in designing PAM4 DSP blocks for FFE, DFE, MLSD, and digital timing recovery.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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