Design Validation Test Engineer
Role summary
We are seeking a Design Validation Test Engineer with 5-10 years of experience to join our team in San Jose, CA. This onsite, 12-month contract role focuses on leading the bring-up and stabilization of complex PCB designs, validating power sequencing, and debugging board-level issues. The engineer will develop and execute Design Validation Test (DVT) plans, including functional, electrical, performance, and stress testing, with a focus on high-speed interfaces like PCIe Gen4/Gen5 and Ethernet. Collaboration with firmware, BIOS, BMC, and driver teams is essential, as is assisting with test automation scripting. The role involves performing root cause analysis on various hardware failures and driving issue resolution through DVT phases.
Job role: Design Validation Test Engineer
Location: San Jose, CA (Onsite)
Duration: 12 Months
Pay Range: $50-$55/hr.
Experience Level: 5 -10 years
JD:
Board Bring Up & Debug
- Lead first power on, early bring up, and stabilization of complex PCB designs
- Validate power sequencing, voltage rails, clocks, resets, and boot paths
- Debug board level issues using schematics, layout, datasheets, and lab instrumentation
- Perform root cause analysis on power, signal integrity, thermal, and functional failures
DVT (Design Validation Test) Execution
- Develop and execute DVT plans covering functional, electrical, performance, and stress testing.
- Validate high speed interfaces (PCIe Gen4/Gen5, Ethernet, SerDes, GT links, DDR/LPDDR, OAM, optical modules).
- Drive corner testing (voltage, temperature, frequency, load conditions).
- Identify, track, and close hardware issues through DVT phases.
System & Firmware Collaboration
Work closely with firmware, BIOS, BMC, and driver teams during bring up.
Support FPGA/SoC configuration, boot flow, and debug (JTAG, XVC, UART, I2C, SPI).
Assist with automation of bring up and test scripts (Python, shell, lab tools).
