Semiconductor ATE Test Engineer
Role summary
The Semiconductor ATE Test Engineer will be responsible for supporting R&D and production testing, interfacing with external vendors, and ensuring test software and hardware align with test plans. Key duties include tracking production yield, managing logistics for ASIC wafers, and developing production methods to enhance efficiency and yield in compliance with TL/ISO manufacturing standards. This hybrid role requires the candidate to work from the Sunnyvale, CA office three days a week and may involve some inter-city travel for off-site testing.
Candidate must be in the Sunnyvale California area
Hybrid: Required to work out of Nokia Sunnyvale CA office 3 days per week.
Will require some inter-city travel to manage off-site testing.
Responsibilities:
• Interface with external vendors for R&D and production testing
• Ensure and correlate test SW and HW to written Test Plan
• Production yield tracking, milestone tracking, problem assessment/disposition and invoice tracking
• Wafer level ATE platform support of production, yield analysis, failure Paretos and yield improvement
• Production logistics including ASIC wafer tracking and travelers
• Supporting engineering releases through pilot runs and production
• Develop, debug and release production methods and procedures to improve efficiency and yield compliant to TL/ISO manufacturing standards
