Staff Hardware Backend Engineer
Role summary
We are seeking a Staff Hardware Backend Engineer with 10+ years of ASIC backend or implementation experience. The role involves developing and maintaining memory wrappers, integration logic, and running critical design flows such as lint, CDC, synthesis, and static timing analysis. You will collaborate with physical design and P&R teams to achieve timing closure and own design release processes. Responsibilities also include supporting SoC integration, resolving interface issues, and automating backend flows with scripting languages like Python, Perl, or Tcl. A BS/MS in Electrical Engineering or a related field is required.
Staff Hardware Backend Engineer (ASIC Implementation / Integration)
Experience:
10+ years
Key Responsibilities
- Develop and maintain
memory wrappers and integration logic
for SRAM/ROM/embedded memories within ASIC/SoC designs.
- Run and maintain
lint, CDC, synthesis, and timing flows
to ensure design quality and sign-off readiness.
- Perform
static timing analysis (STA)
and collaborate with physical design teams to achieve
timing closure
.
- Own and maintain
design release flows
, ensuring clean and consistent handoff of RTL/netlists to downstream teams.
- Support
partner SoC integration
, resolving interface issues and ensuring compatibility with system-level integration requirements.
- Work closely with
P&R teams
to address timing, floorplan, and implementation issues.
- Develop and maintain
automation scripts and infrastructure
for backend flows.
- Support design quality checks including
DFT readiness, constraint validation, and synthesis optimization
.
- Participate in
design reviews and cross-team technical discussions
.
Required Qualifications
- 10+ years of ASIC backend or implementation experience
.
- Strong understanding of
ASIC design flows from RTL to GDS
.
- Experience with
memory macro integration and wrapper development
.
- Strong knowledge of
lint, synthesis, and static timing analysis
.
- Familiarity with industry-standard
EDA tools
, such as:
- Synopsys Design Compiler
- Synopsys PrimeTime
- Cadence Genus
- Cadence Tempus
- Experience supporting
place-and-route (P&R) teams
and addressing implementation issues.
- Experience managing
design release flows and integration deliverables
.
- Strong scripting skills in
Python, Perl, or Tcl
for flow automation.
Preferred Qualifications
- Experience with
large-scale SoC integration
.
- Familiarity with
AMBA interconnect protocols (AXI/AHB/APB)
.
- Experience working with
third-party IP integration and memory compilers
.
- Understanding of
low-power design techniques (UPF/CPF)
.
- Experience with
CDC/RDC verification tools
.
- Familiarity with
DFT requirements and scan insertion flows
.
Education
- BS/MS in Electrical Engineering, Computer Engineering, or related field
.