Senior Software Engineer – Virtual Hardware Modeling

We are currently hiring for a Senior Software Engineer – Virtual Hardware Modeling role in Sunnyvale, CA (Onsite). This opportunity is ideal for engineers with 7–10+ years of experience, including 5+ years in hardware modeling, virtual platforms, or SoC simulation, with strong expertise in SystemC/TLM and modern C++.

Role Overview:

You will be responsible for developing high-level models of complex SoC architectures, enabling system-level simulation, validation, and performance optimization for next-generation hardware platforms.

Key Responsibilities:

• Design and develop SystemC TLM models for SoC components (processors, DSPs, NoC, DMA, memory controllers)

• Integrate vendor and in-house models into virtual platforms with automation and CI workflows

• Develop high-performance C++ models for hardware accelerators

• Collaborate with architects, designers, and verification teams for end-to-end silicon validation

• Enable performance and power analysis through model instrumentation

Required Skills:

• Strong proficiency in modern C++ (simulation / EDA / chip design domain)

• Experience with SystemC / TLM

• Hands-on with virtual platform tools (Synopsys Virtualizer, Cadence, ARM Fast Models, Imperas OVP)

• Understanding of SoC architecture (ARM, RISC-V, DSPs, NoC, MMU, cache)

• Experience with C++ concurrency (threads, atomics, memory models)

• Proficiency in Python for automation