Sr. ASIC Design Verification Engineer (Starshield)

Hawthorne, California, United StatesOnsiteFull TimeSenior$160,000–$225,000 /yrPosted 2 months agoVisa sponsorship available

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Role summary

SpaceX is seeking a Sr. ASIC Design Verification Engineer for its Starshield program, focusing on national security applications leveraging Starlink technology. This role involves developing and verifying next-generation FPGAs and ASICs for space and ground infrastructure. Responsibilities include leading digital ASIC verification at block and system levels, developing SystemVerilog testbenches (UVM/non-UVM), executing test plans, achieving coverage closure, and automating test case generation using Python and MATLAB. The position requires a Bachelor's degree in EE, CE, or CS, with 5+ years of experience in design verification and testbench development. Experience with UVM/OVM/VMM, constrained random verification, and chip bring-up/validation is preferred.

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD)

Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Verification Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

Responsible for digital ASIC verification at block and system level

Lead and execute verification test plan, development, and milestones from beginning to end, develop test harnesses and test sequences

Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks

Responsible for test plan execution, running regressions, code and functional coverage closure

Automate test case generation by using Python and MATLAB programs

Contribute to pre-silicon verification, chip bring-up and post-silicon validation

Be a hands-on self-starter who can execute the steps required to fully verify complex digital designs

BASIC QUALIFICATIONS:

Bachelor’s degree in electrical engineering, computer engineering, or computer science

5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

Advanced degree in electrical engineering or computer engineering

Experience with verification methodologies such as UVM/OVM/VMM

Strong object-oriented programming knowledge

Strong problem-solving and coding skills

Experience in constrained random verification

Expertise in developing test plans, implementing coverage models, and analyzing results

Experience with scripting languages, e.g. Python for automation

RTL design, chip bring-up, and post-silicon validation experience

Ability to work in a dynamic environment with changing needs and requirements

Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis

Enjoy being challenged and learning new skills

ADDITIONAL REQUIREMENTS: 

Ability to work long hours and weekends as necessary to support critical milestones 

Willingness to travel for off-site testing

An active clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing

COMPENSATION AND BENEFITS: Pay range: Sr. ASIC Design Verification Engineer: $160,000.00 - $225,000.00/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.
ITAR REQUIREMENTS:

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

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