
SoC Physical Design Engineer, PnR
Role summary
Apple is seeking a SoC Physical Design Engineer specializing in Place and Route (PnR) to be responsible for the physical implementation of highly complex SoC designs from netlist to tapeout. This role involves working closely with logic design teams, completing PnR implementation, performing timing, physical, and electrical verification, and driving signoff closure. The engineer will also resolve design and flow issues and optimize PnR partitions for best Power/Performance/Area. The position requires a minimum of BS and 3+ years of relevant industry experience, with a preference for candidates with recent successful deep submicron technology tapeouts and strong knowledge of PD flows and methodologies.
Description
• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical verification, and driving the signoff closure for the partitions. • Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution. • Drive optimization of PnR partitions, to achieve best Power/Performance/Area.
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience.
Preferred Qualifications
Recent successful tapeouts in deep submicron technology. Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution, timing closure, and physical & electrical verification. Strong knowledge of PD construction & analysis flows and methodology. Shown ability to execute to stringent schedule & die size requirements. Strong interpersonal skills. Experienced in industry standard tools and understanding their capabilities and underlying algorithms.
Sample Apple interview questions
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