Senior Software Engineer - Virtual Hardware Modeling
Role summary
Seeking a Senior Software Engineer with expertise in virtual hardware modeling. The role requires high proficiency in modern C++ within chip design, EDA, or simulation domains, along with experience in SystemC/TLM. Familiarity with virtual platform development tools like Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models is essential. The position also demands knowledge of processor/DSP architectures (ARM, RISC-V, XTensa), low-level hardware concepts (NoC, MMU, cache modeling), and C++ concurrency. Proficiency in Python for automating design flows and creating collateral data is also required. This is an onsite, full-time position in Sunnyvale, CA.
Opening for Software engineer- Virtual hardware Modeling- Sunnyvale CA- Onsite.
Role: Senior Software Engineer - Virtual Hardware Modeling
Work location: Sunnyvale CA- Onsite
High proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation.
• Experience with the SystemC/TLM library
• Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models
• Familiarity with processor/DSP architectures, such as ARM, RISC-V, and XTensa
• Familiarity with NoC, MMU, address translations, and cache modeling
• Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc…
• Proficiency in Python to automate design flows, creation of collateral data"
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