Software Engineer - Virtual Hardware Modeling

Name: RiseMe
Availability: InStock

California, United StatesOnsiteContractPosted 2 months agoVisa sponsorship available

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Role summary

This role involves designing and developing high-fidelity SystemC TLM models for System-on-Chip (SoC) architectures, including processors, DSPs, and memory controllers. The engineer will integrate various models into a virtual platform, automate workflows for accuracy and connectivity, and collaborate with cross-functional teams. Key responsibilities include enhancing virtual platforms for architecture exploration, power/performance analysis, and enabling end-to-end silicon validation. The position requires strong C++ and Python skills, experience with virtual platform tools, and familiarity with processor architectures and hardware modeling concepts.

Responsibilities

• Design and develop SystemC TLM models to accurately represent the SoC architecture integrating emulated processors, DSPs, Network-on-Chip, DMA and memory controllers, etc…

• Integrate first-party and vendor models into the Virtual Platform, develop automated workflows to ensure register-level accuracy and complete connectivity at the SoC level, minimizing manual intervention and enabling continuous integration.

• Collaborate with silicon architects, digital designers and verification engineers to design and develop high-fidelity, fast C++ models for first-party IP.

• Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering, enabling end-to-end silicon validation test frameworks.

• Enhance the virtual platforms to enable SoC and system architecture exploration by instrumenting models for power and performance metrics, allowing for data-driven design decisions and trade-off analysis to optimize system performance and power consumption.

Minimum qualifications

• B.S. degree in Computer Science or Electrical Engineering or equivalent experience.

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• 7-10+ years of experience with 5+ years experience in hardware model simulation, virtual platform, performance modeling of complex SoCs or high-fidelity hardware accelerators.

• High proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation.

• Experience with the SystemC/TLM library

• Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models

• Familiarity with processor/DSP architectures, such as ARM, RISC-V, and XTensa

• Familiarity with NoC, MMU, address translations, and cache modeling

• Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc…

• Proficiency in Python to automate design flows, creation of collateral data

Key Responsibilities:

"• Design and develop SystemC TLM models to accurately represent the SoC architecture integrating emulated processors, DSPs, Network-on-Chip, DMA and memory controllers, etc…

• Collaborate with silicon architects, digital designers and verification engineers to design and develop high-fidelity, fast C++ models for first-party IP."

What are the Mandatory skills and skill proficiencies required for this position?

"High proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation.