Verification Engineer II

KentuckyOnsiteFull Time$120,000–$160,000 /yrPosted 5 days agoVisa sponsorship available

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Required skills

SoC
video
image processing
computer vision
AI applications
RTL
simulation
regression

Nice to have

agentic AI verification flows
directed tests
assertions
coverage models
Python scripts
utilities

Role summary

Ambarella is seeking a motivated Verification Engineer for advanced SoCs in video, image processing, computer vision, and AI. Responsibilities include developing and executing verification solutions using SystemVerilog, UVM, Verilog, C/C++, and Python. You will create testbenches, verification plans, directed/random tests, and leverage AI for test generation and debugging. The role requires strong digital logic design and computer architecture understanding, with familiarity in UVM and constrained-random testing. Python and/or C/C++ programming skills are essential. This contract role offers competitive benefits and the potential for conversion to full-time.

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Ambarella is seeking a motivated Verification Engineer to develop and execute verification solutions for advanced SoCs used in video, image processing, computer vision, and AI applications.

You will work with established verification methodologies and modern agentic AI verification flows to develop tests, analyze failures, improve coverage, and accelerate debugging.

Key Responsibilities

Develop and maintain verification testbenches using SystemVerilog, UVM, Verilog, C/C++, and Python.
Create and execute verification plans for DSP blocks, control logic, processor cores, and specialized accelerators.
Verify components of Ambarella's image processing pipeline, video input subsystem, compression engines, and neural network processors.
Develop directed and constrained-random tests, assertions, checkers, and coverage models.
Debug RTL and testbench failures, analyze simulation results, and resolve coverage gaps.
Use and enhance agentic AI verification workflows for test generation, failure analysis, coverage improvement, and debugging automation.
Develop Python scripts and utilities to automate verification and regression tasks.
Collaborate with RTL design, architecture, and software teams.

Qualifications

At least Bachelor’s (preferably Master's) degree in Electrical Engineering, Computer Engineering, or a related field.
Strong understanding of digital logic design and computer architecture.
Hands-on experience with Verilog/SystemVerilog and simulation-based verification.
Familiarity with UVM, constrained-random testing, and functional coverage.
Programming skills in Python and/or C/C++.
Strong debugging, problem-solving, and communication skills.

The base range is $120,000-$160,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits

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