Design Verification Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Understand the design specification and extract attributes of the design from the specification. Create UVM based tests and sequences based on attributes to stress the design and verify correctness of the RTL. Have discussions with Design Engineers regarding missing specifications, corner cases/interesting scenarios where the design might show unexpected behavior. Debug root cause of failure and reporting the bug to design engineer using waveform analysis/log files. Work with EDA vendors to use VIP/tool in our test benches. Develop Coverage points to analyze coverage and writing Assertions for the design. Understand the design, extracting attributes from the design specification and verifying correctness of the RTL design. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Electrical and Computer Engineering or related field. Experience and/or education must include: Experience in Hardware Verification Language (HVL) and Hardware Design Language (HVL) including System Verilog or Verilog for Verification Environment and test development. Utilizing knowledge of HVL methodology (UVM, OVM, and VMM) for constrained random test development. Applying verification skills in problem solving, constrained random testing, and debugging. Understanding of reusable verification framework to help speedup verification process. Utilizing knowledge of digital logic design, chip architecture and microarchitecture to help analyze and debug RTL design. Applying AMBA protocol knowledge in developing monitor/checker and analyzing RTL design System Verilog Assertion (SVA) for verification. Programing in C/C++ for embedded CPU verification and system modeling Writing scripts in languages including Perl or Python. Defining coverage space and writing coverage model to measure verification quality and find verification holes.

Preferred Qualifications

N/A