Physical Design Engineer
Required skills
- Clock Implementation
- Clock Architecture
- High-speed clock distribution
- Spice
- Excel
- Clock planning
- Power domain
- Routing congestion
- Placement constraints
- Clock repeater studies
Nice to have
- Custom clock cell design
Role summary
Apple Inc. is seeking a Physical Design Engineer in Austin, Texas, to work on graphics projects involving clock implementation across multiple clock domains. Responsibilities include clock architecture, designing high-speed clock distribution circuits, clock planning, building simulation models using Spice, and interacting with floorplan owners. The role involves clock repeater studies, analyzing buffer configurations, and defining custom clock cells. The engineer will optimize clock trees for performance and reliability, manage synchronization and isolation across domains, and debug physical design verification issues like DRC and LVS.
Description
APPLE INC has the following available in Austin, Texas. Work on graphics projects from start to end for clock implementation which involve multiple clock domains. Work on clock architecture and designing high speed clock distribution circuits; Responsible for clock planning, building simulation models (Using Spice), & interacting with Floorplan owner to understand any Power domain/routing/placement challenges for the clocking. Involve in Clock repeater studies for a certain process technology with different size buffer, fanout, metal spec studies were done (Using Spice) and tabulated in excel for implementation engineer to choose right cell and layer based on nature of clock; and Involving in Clock cell definition and sizes and family of custom clock cell needed for a particular process technology. 40 hours/week.
Minimum Qualifications
Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field and 1 year of experience in the job offered or related occupation. 1 year of experience with each of the following skills is required: Build high-speed clock distribution networks optimized for performance and reliability Implement designs across multiple clock domains with proper synchronization and isolation Execute clock planning with considerations for power domains, routing congestion, and placement constraints Optimize clock trees to minimize latency and skew for high-performance designs Analyze and select clock repeater and buffer configurations across various process technologies Tune metal layer usage and fanout strategies to enhance clock signal integrity and timing Debug physical design verification (PDV) issues such as DRC, LVS, shorts, and opens during clock construction
Preferred Qualifications
N/A
Sample Apple interview questions
- 1
Design a typeahead box for a search engine
system designmedium - 2
Design a rate limiter
system designmedium - 3
Architect a key-value store for distributed systems.
system designmedium - 4
Design a system to schedule jobs in a distributed environment
system designmedium - 5
What is an API and how does it work?
technicalmedium
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