Verification Platform Engineer, Platform Architecture

Name: RiseMe
Availability: InStock

Austin, TXOnsiteFull TimePosted 2 months agoVisa sponsorship available

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Required skills

SystemVerilog
EDA tooling
C++
Perl
Python
UVM
DPI-C
testbench architecture

Nice to have

Master’s degree
LEC
linting
static analysis
waveform debugging
simulation

Role summary

Apple's Platform Architecture group is seeking a Verification Platform Engineer to develop high-performance verification systems for Apple silicon. This role involves bridging platform technology with Design Verification (DV) methodology and tooling, focusing on improving simulation throughput through testbench design, infrastructure enhancements, and platform R&D. The ideal candidate will have experience with SystemVerilog, EDA tools, software development (C++), and scripting (Perl/Python), with a strong background in DV methodologies like UVM. Preferred qualifications include a Master's degree, 10+ years of experience, and expertise in areas like HPC, co-simulation, or AI productivity tools for engineers.

Apple’s Platform Architecture group develops the next generation of Apple hardware and the tools to make it possible. Our team builds high-performance verification systems that accelerate the development of Apple silicon. We aim to push the boundaries of pre-silicon validation with simulation solutions that apply and extend principles from hardware emulation.

Description

This role bridges Apple's next-generation platform technology with DV methodology and tooling. We are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping solutions. In this role, you will enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.

Minimum Qualifications

Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience). Experience with SystemVerilog and EDA tooling. Experience with software development (e.g., using C++) and scripting (e.g., Perl or Python).

Preferred Qualifications

Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field. 10+ years of relevant experience. Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture). Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows. Strong understanding of SystemVerilog simulation semantics (events, time, glitches); intuitive grasp for hardware representation (clocks, resets, latches). Strong communication skills, with a proven history of cross-functional collaboration across silicon engineering, design verification, and EDA development teams and organizational boundaries. Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration / emulation. Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers.

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