RFIC Layout Engineer

Do you have a passion for invention and self-challenge? Do you thrive with pushing the limits of what’s considered feasible? As part of an outstanding `team, you’ll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a single, coordinated design. Join us, and you’ll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide.

Description

Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering. - Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking. - Co-work with designers on block-level and top-level floorplanning. - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling. - Top-level layout integration and verification, schedule management.

Minimum Qualifications

Minimum requirement of a bachelors degree Understanding of RC delay, electromigration, and coupling. Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Good communication skills and ability to work with multi-functional teams.

Preferred Qualifications

Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience). Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing. Good understanding of RC delay, electromigration, and coupling. Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology. Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools.