
Packaging Engineer
Required skills
- Packaging Engineer
- Custom Silicon packaging
- consumer markets
- product/device design
- quality
- supply chain
- external suppliers
- new packaging technologies
- negotiator
- influencer
Nice to have
- M.S
- mechanical engineering
- physics
- materials science
- AutoCAD
- APD
Role summary
Seeking a senior-level Individual Contributor Packaging Engineer to develop innovative Custom Silicon packaging solutions for consumer markets. This role involves interfacing with internal teams and external suppliers to deploy new packaging technologies, reduce development cycles, and qualify devices for high-volume manufacturing. The ideal candidate will have a strong background in IC packaging, qualification, reliability testing, and process development, with expertise in areas like WLP, Wafer Bumping, and assembly processes. Experience with simulation tools and materials science is preferred.
Description
• In this fast-paced environment, your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies. • Must be a good negotiator and influencer to drive industry to meet company needs. • We are looking for individuals who are very innovative with a proven track record to reduce package development cycle and qualify devices into a high-volume manufacturing environment.
Minimum Qualifications
BS and 10+ years of relevant industry experience.
Preferred Qualifications
M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 10 years of experience in IC packaging. AutoCAD, APD and multi-physics simulation knowledge is a plus. Industry experience and work on WLP either in IDM or Fabless companies. Knowledge and hands-on experience on Wafer Bumping and Dielectric materials and their pros/cons is a must. Some hands-on knowledge in Manufacturing assembly processes; such as wafer back-grind, wafer dicing, Flip Chip die attach, encapsulation/molding, under-fill, ball attach, package singulation and Tape & Reel. In-depth knowledge in Wafer Level Chip Scale Packaging (RDL/Wafer Bumping & BEOL Assembly processes for Fan-In & Fan-Out designs). Good knowledge on Package Qualification and Reliability testing. Expert level knowledge of common reliability failure modes. Able to understand device physics and component/board level reliability testing. Proven track record to bring a product/package from conceptual stage to development and to HVM environment. Ability to construct Designs of Experiments and down-select materials and processes. Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at team meetings and executive review meetings. Able to perform independent research and development work with minimal supervision.
Sample Apple interview questions
- 1
Design a typeahead box for a search engine
system designmedium - 2
Design a rate limiter
system designmedium - 3
Architect a key-value store for distributed systems.
system designmedium - 4
Design a system to schedule jobs in a distributed environment
system designmedium - 5
What is an API and how does it work?
technicalmedium
Get started to unlock a personalized interview prep pack for this role.
Similar roles
Learning Experience Designer, WW Sales Learning & DevelopmentApple · Austin, TX · Onsite
Graphics Software EngineerApple · Austin, TX · Onsite
Sr. Manager Packaging EngineeringAMD · Santa Clara, CA · Onsite- Senior Hardware Product Packaging EngineerSkydio · San Mateo, CA · Hybrid
- Packaging Engineer IIHelloFresh · New York, NY · Onsite
Sr. Packaging EngineerPregis · Aurora, IL · Onsite
