
SRAM Circuit Design Engineer
Required skills
- SRAM
- Circuit Design
- Digital Circuits
- SRAM design
- logic/architecture team
- architecture
- topologies
- power
- timing
- area
Nice to have
- SoC design cycle
- SRAM/Register File
- low power
- low voltage
- high performance
- Cache design
Role summary
Join a world-class silicon design team as an SRAM Circuit Designer. You will craft entirely new solutions, turning imaginative ideas into reality by designing and implementing custom digital circuits for SRAM. This highly visible role involves defining architecture, optimizing for power, timing, area, and yield, performing schematic capture, simulations, and verification. You will collaborate with logic/architecture and layout teams, support post-silicon efforts, and contribute to groundbreaking techniques in areas like Machine Learning. A minimum of 3 years of relevant industry experience is required, with preferred experience in SoC design cycles, cache design, RTL modeling, device physics, and silicon debug.
Description
Imagine yourself at the center of our hardware development effort. Where you will collaborate with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come up with new insights, work with a team of hardworking engineers, and implement groundbreaking techniques of Machine Learning, Circuit design in Apple’s marquee products like M1 and A14 Bionic. As an SRAM Circuit Designer for the Digital Custom Group, you will perform the following: - Design and implement custom digital circuits for SRAM design. - Work with an extraordinary logic/architecture team to formulate design specifications. - Define architecture/topologies optimizing for power, timing, area and yield. - Schematic capture, simulations/analysis, margin verifications. - Functional equivalency and DFT modeling. - Work with layout team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL, validate use-cases, verify against design schematics. - Support post-silicon effort to enable productization.
Minimum Qualifications
BS and a minimum of 3 years relevant industry experience.
Preferred Qualifications
We are looking for applicants with work experience within a SoC design cycle, developing circuits and SRAM/Register File for low power, low voltage and high performance. Knowledge of Cache design/architecture, memory hierarchy is a huge plus. Working knowledge of RTL modeling. Solid understanding of industry-standard design tools. Deep understanding of nanometer device physics, leakage mechanisms, technology interactions with device behavior. Ability to devise experiments and analyze data for silicon debug. Machine Learning algorithms (ML) and scripting is a big plus.
Sample Apple interview questions
- 1
Design a typeahead box for a search engine
system designmedium - 2
Design a rate limiter
system designmedium - 3
Architect a key-value store for distributed systems.
system designmedium - 4
Design a system to schedule jobs in a distributed environment
system designmedium - 5
What is an API and how does it work?
technicalmedium
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