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Semiconductor, AI Infrastructure, Cloud Computing, Hardware

Principal Emulation Engineer

San Jose, CAOnsiteFull TimePrincipal$207,000–$230,000 /yrPosted 1 month agoVisa sponsorship available

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Required skills

  • ASIC
  • SoC
  • RTL
  • hardware-software interactions
  • high-speed protocols
  • PCI Express Gen 3
  • Ethernet
  • DDR
  • NVMe
  • SPI

Nice to have

  • CXL
  • UALink
  • Palladium
  • Zebu
  • Veloce
  • HAPS

Role summary

Astera Labs is seeking a Principal Emulation Engineer in San Jose, CA, to build and operate emulation environments for complex ASICs and SoCs. This role involves architecting and integrating RTL, transactors, and software to stress-test hardware-software interactions and high-speed protocols like PCIe, Ethernet, DDR, and NVMe. The engineer will partner with cross-functional teams to debug issues, provide technical leadership, and ensure product milestones are met. Requires a Bachelor's degree in a technical field, 8-12 years of experience in SoC development, and proficiency in SystemVerilog and scripting languages like Python. Experience with emulation platforms is preferred.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Principal Emulation Engineer — San Jose, CA

Role Overview

As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn difficult debug problems into actionable fixes and improve confidence in each product milestone.

Astera Labs is accelerating the infrastructure behind AI by delivering purpose-built connectivity solutions for rack-scale systems. In this role, you’ll help validate the switching, PCIe, Ethernet, memory, and storage interfaces that connect the compute fabric—enabling faster bring-up, stronger interoperability, and more reliable platforms as the company scales.

Key Responsibilities

  • Emulation and Prototyping
  • Architect, build, and maintain emulation environments for complex ASICs and SoCs.
  • Integrate RTL, transactors, protocol models, software, and test infrastructure to enable meaningful hardware-software co-simulation.
  • Enable verification teams to stress-test designs with scalable, repeatable emulation workflows.
  • Develop reusable models, utilities, and debug methodologies that accelerate pre-silicon validation.
  • Protocol and SoC Verification
  • Verify hardware-software interfaces and system behaviors in partnership with logic designers, firmware engineers, and verification teams.
  • Exercise and debug PCI Express Gen 3 and above, Ethernet, DDR, NVMe, SPI, I2C/I3C, and similar interfaces.
  • Analyze protocol behavior, functional coverage, performance, and corner cases across complex server, storage, and networking systems.
  • Translate system requirements into practical emulation scenarios, tests, checkers, and measurable verification goals.
  • Debug and Technical Leadership
  • Debug design, environment, transactor, software, and test-code issues across the emulation stack.
  • Identify software and hardware co-simulation limitations and apply effective isolation and debug techniques.
  • Partner with cross-functional teams to prioritize a dynamic workload, resolve issues quickly, and drive risks to closure.
  • Provide technical leadership, communicate clearly, and operate effectively with minimal guidance and supervision.

    • Basic Qualifications

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
  • 8–12 years of experience supporting or developing complex SoC or silicon products for server, storage, or networking applications.
  • Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
  • Working knowledge of PCI Express Gen 3 or later, CXL, UALink, Ethernet, DDR, NVMe, SPI, I2C/I3C, or similar communication protocols.
  • High proficiency in SystemVerilog and hardware verification environments.
  • Experience understanding software and hardware co-simulation limitations and applying effective debug methods.
  • Programming and scripting experience in Python, Perl, C, or similar languages.
  • Professional, entrepreneurial, and open-minded approach with a can-do attitude, strong prioritization skills, and a customer-focused mindset.
  • Authorized to work in the United States and available to start immediately.

    • Preferred Qualifications

  • Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
  • Hands-on experience with Palladium, Zebu, Veloce, HAPS, FPGA prototyping, or similar emulation and prototyping technologies.
  • Experience developing models for emulation and prototyping and working in non-UVM verification environments.
  • Experience building protocol transactors, behavioral models, software drivers, or system-level validation infrastructure.
  • Based in the San Jose area or open to relocation; comfortable working fully in person.

    • Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

    We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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