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Biotechnology, Artificial Intelligence, Healthcare Technology, Life Sciences

EDA and CAD Lead Engineer / Manager

Menlo ParkOnsiteFull TimeLeadPosted 10 days ago

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Required skills

  • EDA
  • CAD
  • mixed-signal ICs
  • ASIC design
  • layout
  • floor planning
  • IP integration
  • pad ring
  • analog/mixed-signal designers
  • high-performance layout

Nice to have

  • CMOS
  • SiGe Process Development Kits
  • multidisciplinary team
  • RF
  • Mixed Signal
  • Hardware

Role summary

Seeking an experienced EDA/CAD Lead Engineer/Manager for a mixed-signal IC design team. This hands-on role involves floor planning, IP integration, LVS/DRC checks, and collaborating with design teams from concept to production. Requires 5+ years of CMOS IC implementation experience and strong proficiency with Cadence tools (Virtuoso, Calibre, Voltus), scripting languages (Tcl, Python, Perl, Makefile, shell), and DFT/ATPG. A formal Cadence digital layout training/certification is required. Preferred skills include experience with CMOS/SiGe PDKs and multidisciplinary teams. The position offers a competitive salary and benefits.

We are seeking an experienced EDA/CAD lead engineer to join our growing team. In this role, you will be part of the experience design and layout team to develop cutting-edge mixed-signal ICs. You will be involved in the technical aspects of the ASIC design and development, from concept through to production. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals.

Key Responsibilities:

  • Floor planning, IP integration
  • Pad Ring creation
  • Work with analog/mixed-signal designers for high-performance layout integration
  • Work with digital designers for DFT/ATPG/Scan logic integration
  • Perform LVS/DRC checks and fix issues
  • Integration of Digital/RF/mmWave blocks into IC Top Level
  • Collaborate with cross-functional teams to ensure timely project execution and design tape-outs
  • Stay updated with the latest trends and technologies in wideband high speed IC design and apply them to improve project outcomes
  • Occasional travel to the Bay Area (<20%) for remote position

    • Qualifications:

  • 5+ years of hands-on experience in CMOS (bulk and advanced FinFET) IC implementation in multiple process technologies
  • Strong experience with Cadence (and various EDA) tools is required (Virtuoso, Calibre, Voltus)
  • Experience in multiple dedicated tapeout support is required
  • Scripting language experience in Tcl, Python, Perl, Makefile, and shell scripts are required

    • Education:

  • Formal Cadence digital layout training or certification is required
  • Bachelor’s degree in electrical engineering, computer science or a related field is preferred

    • Preferred Skills:

  • Experience with CMOS, and/or SiGe Process Development Kits
  • Experience working on a multidisciplinary team with RF/Mixed Signal, Hardware, Firmware, and Software engineers
  • Strong communication and teamwork skills
  • Experience working in fast-paced environments with a strong track record of delivering high-quality designs on time.

    • Benefits:

  • Competitive salary
  • Stock options plan
  • Paid time off
  • Health benefits
    • Ready to apply?
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