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Semiconductor, Electronic Design Automation (EDA), Software Development

Application Engineer Architect (STA SignOff)

RemoteRemoteFull TimeDistinguished / Architect$154,000–$286,000 /yrPosted 24 days agoVisa sponsorship available

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Required skills

  • STA
  • ECOs
  • UPF
  • 3DIC
  • Tcl
  • Python
  • Perl
  • IR Drop
  • AgenticAI
  • IC design implementation

Nice to have

  • Tempus
  • Certus
  • QRC
  • competitive solutions

Role summary

Cadence is seeking an Application Engineer Architect with 15+ years of experience in IC design implementation and signoff, particularly for advanced nodes (5nm and below). The role involves leading technical engagements with customers and partners, driving adoption of Cadence's signoff portfolio, and influencing R&D based on customer requirements. Responsibilities include optimizing flows, deploying methodologies for timing signoff, STA, IR Drop, and power/timing closure. The position requires deep expertise in digital design fundamentals, advanced node STA & ECOs, EDA tool ecosystems, and scripting languages like Tcl, Python, and Perl. Experience with Cadence tools is highly desirable. This role emphasizes thought leadership through industry presentations and technical papers.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

  • Technical Expertise: Lead technical engagements with customers and partners to drive & adoption of Cadence signoff portfolio. Work closely with design teams to meet customer success metrics, guide adoption of Cadence’s timing signoff & closure and AgenticAI features across advanced nodes (5nm and below).
  • Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
  • Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing sigoff & closure, STA, IR Drop, and power/timing closure.
  • Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Qualifications

  • 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems.
  • Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
  • Proven track record of leading technical teams and driving customer success at executive levels.
  • Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
  • Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
  • Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable.

The annual salary range for Washington is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

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