Physical Design Engineer, FullChip/ASIC Implementation

Mountain View, CAOnsiteFull Time$138,000–$197,000 /yrPosted 2 months agoVisa sponsorship available

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Required skills

Physical Design
ASIC
RTL2GDS
PPA
High Performance
Power
Area
Full-chip implementation
STA
Sign-off

Nice to have

Floorplanning
Block integration
Low power design
UPF
CPF
Multi-voltage domains

Role summary

Google is seeking a Physical Design Engineer to join their team developing custom silicon solutions for direct-to-consumer products. This role involves full-chip ASIC implementation, focusing on high performance, power, and area (PPA). You will contribute to the innovation of next-generation hardware experiences, delivering unparalleled performance and efficiency. The position requires a Bachelor's degree in Electrical Engineering or equivalent experience, with a minimum of 4 years in physical design and experience with synthesis/PnR tools.

Minimum qualifications:

Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience in physical design.
Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.

Preferred qualifications:

Experience in top-level floorplanning and block integration.
Experience in low power design implementation including UPF/CPF, multi-voltage domains and power gating.
Experience with ASIC design flows and methodology of physical design.
Understanding of circuit design, device physics, and deep submicron technology.
Knowledge of Verilog/SystemVerilog and fundamentals of computer architecture.
Effective skills with scripting languages such as Tcl, or Perl.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
Manage full-chip level physical implementation.
Define and implement innovative schemes to improve performance and power.
Work with cross-functional teams to deliver best quality of results.

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