ADCE Packaging Design Architect
Required skills
- electrical analysis
- semiconductor fabrication
- packaging
- analytical ability
- debug
- Mentor
- Cadence tools
- SPICE
- Ansys tools
- Cadence Allegro
Nice to have
- assembly process
- test
- characterization techniques
Role summary
Seeking an experienced ADCE Packaging Design Architect with a strong background in semiconductor fabrication and packaging. This role involves driving end-to-end substrate design, implementing physical layout and routing, and performing trade-off studies. The architect will collaborate with silicon and hardware teams to optimize performance and pinout, define design rules, conduct reviews, and resolve design rule checks (DRCs). A Ph.D./Master's in a relevant engineering field or Material Science with 10+ years of experience in Package, PCB, or IC digital design is required. Proficiency with design and simulation tools like Mentor, Cadence, SPICE, and Ansys is essential.
Job Details:
Job Description:
Drives end-to-end development for substrate design from concept through tape out and implements physical layout and routing of the package design. Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs. Works closely with silicon and hardware teams to optimize silicon-package-board performance and pinout. Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design. Completes documentation and collateral into the product lifecycle management system of record.
Required Skills and Experience:
- Self-motivated engineer who has strong technical background in design and electrical analysis.
- Solid background in semiconductor fabrication and packaging
- Strong analytical ability and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions. - Ability to work independently and at various levels of abstraction
- Strong organization, time management, and communication skills, self-motivated.
- Experience with design and electromagnetic simulation tools: Mentor, Cadence tools, SPICE, Ansys tools etc.
- Experience in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity), and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
- Experience and knowledge with assembly process, test and characterization techniques preferred
Qualifications:
- Ph.D./master’s in electrical engineering/ chemical engineering/ mechanical engineering or Material Science.
- 10+ years and in-depth knowledge/background in Package, PCB design, or IC digital design.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, Arizona, PhoenixAdditional Locations:
US, California, Folsom, US, California, Santa Clara, US, Colorado, Fort Collins, US, Massachusetts, Beaver Brook, US, New Mexico, Albuquerque, US, Oregon, Hillsboro, US, Texas, Austin, US, Washington, Multiple CitiesPosting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 06/09/2026*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Sample Intel interview questions
- 1
Create an installment payment platform for Intel.
system designmedium - 2
Design a distributed job queue.
system designmedium - 3
Design a link shortening service similar to TinyURL.
system designmedium - 4
Design a system for real-time customer feedback analysis.
system designmedium - 5
How would you architect a scalable platform for processing data from millions of IoT devices in real-time?
system designmedium
Get started to unlock a personalized interview prep pack for this role.
Similar roles
- Supply Chain Integrator – (Contract)Intel · Aloha, OR · Hybrid
- Factory Construction Project / Program ManagerIntel · Johnstown, OH · Onsite
- Metagame Design ArchitectLevel99 Entertainment · Greater Boston, MA · Hybrid
- Remote Senior Interior Design ArchitectThe Hello Team · Remote · Remote
- Mixed-signal Design Architect, HBM ArchitectureMicron Technology · Folsom, CA · Onsite
Digital Design Architect HPC IP - 18388Synopsys · Austin, TX · Onsite
