Meta Verified
Social Media, Technology, Virtual Reality, Advertising
AI Systems Engineer, Hardware Architecture
RemoteHybridFull Time$260,000–$319,000 /yrPosted 1 month agoVisa sponsorship available
Required skills
- AI Systems Engineer
- Hardware Architecture
- AI-accelerated computing
- silicon roadmap
- systems roadmap
- on-device AI inference
- training workloads
- wearables
- headsets
- spatial computing
Nice to have
- custom silicon development flows
- architecture-to-RTL handoff
- physical design constraints
- post-silicon validation
- power-constrained
- area-constrained
Role summary
Meta Reality Labs is seeking a principal AI Systems Engineer to define the hardware architecture strategy for next-generation AI-accelerated computing systems for VR/AR products. This role involves shaping the silicon and systems roadmap for on-device AI inference and training, driving architectural decisions across custom silicon, memory, interconnects, and co-design. The engineer will lead system-level exploration, develop performance models, and ensure hardware remains at the forefront of performance and efficiency for immersive computing. Responsibilities include defining roadmaps, driving cross-functional alignment, mentoring engineers, and representing hardware architecture in executive reviews.
Meta Reality Labs is seeking a principal-level AI Systems Engineer to define the hardware architecture strategy for next-generation AI-accelerated computing systems powering virtual and augmented reality products. In this role, you will shape the long-term silicon and systems roadmap for on-device AI inference and training workloads across wearables, headsets, and spatial computing platforms. You will drive architectural decisions that span custom silicon, memory subsystems, interconnects, and software-hardware co-design, ensuring Meta's AI hardware remains at the forefront of performance, efficiency, and capability for immersive computing experiences.
Responsibilities
Minimum Qualifications
Preferred Qualifications
$260,000/year to $319,000/year + bonus + equity + benefits
Responsibilities
- Define and own the multi-year architectural roadmap for AI compute subsystems across Meta's hardware product lines, including wearables and spatial computing devices
- Lead system-level architecture exploration for AI inference and training accelerators, including memory hierarchy design, interconnect topology, and power-performance-area tradeoffs
- Drive cross-functional alignment across silicon engineering, firmware, software, and product teams to translate AI workload requirements into hardware specifications
- Develop and maintain architectural models, performance simulators, and analytical frameworks to evaluate design tradeoffs at the system level
- Identify and resolve architectural bottlenecks across the AI compute stack, from neural network operators to silicon microarchitecture
- Establish technical direction for AI hardware platform decisions, including custom silicon versus third-party IP evaluation and integration strategies
- Partner with machine learning researchers and compiler teams to co-design hardware-software interfaces that maximize AI model efficiency on constrained wearable platforms
- Represent hardware architecture in executive-level technical reviews, authoring detailed architecture decision records and system specifications
- Mentor and provide technical guidance to other engineers across hardware architecture and systems engineering disciplines
- Evaluate emerging AI workloads, model architectures, and compute paradigms to proactively inform future hardware platform investments
Minimum Qualifications
- 15+ years of experience in hardware systems architecture, with a focus on AI, ML, or high-performance compute systems
- Experience defining SoC or system-level architecture for AI inference or training workloads, including memory subsystem design, compute hierarchy, and interconnect topology
- Experience with hardware-software co-design methodologies for on-device AI workloads, including familiarity with ML compiler stacks, operator fusion, and quantization impacts on hardware design
- Experience developing system performance models and using simulation or analytical frameworks to evaluate architectural trade-offs at scale
- Track record of driving multi-year hardware architecture roadmaps and influencing silicon strategy across large engineering organizations
Preferred Qualifications
- Familiarity with custom silicon development flows, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation feedback loops
- Experience architecting AI systems for power- and area-constrained wearable or mobile devices, including VR headsets, AR glasses, or similar spatial computing platforms
- Experience in evaluating and integrating emerging memory technologies (e.g., HBM, LPDDR5X, in-memory compute) into AI system architectures
- Background in collaborating with ML research teams to translate novel model architectures into hardware-efficient deployment targets
$260,000/year to $319,000/year + bonus + equity + benefits
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