Meta Verified
Social Media, Technology, Virtual Reality, Advertising
Digital Design Engineer, SoC Chassis
Sunnyvale, WAOnsiteFull Time$146,000–$209,000 /yrPosted 1 month agoVisa sponsorship available
Required skills
- ASIC
- digital microarchitecture
- RTL coding
- IP integration
- hardware design engineer
- production silicon
- volume shipping
- microarchitecture development
- performance analysis
- power analysis
Nice to have
- infrastructure IP
- clock generation
- power management
- subsystem-level implementation
- subsystem integration
- microcontroller clusters
Role summary
Meta is hiring Digital Design Engineers for SoC Chassis to develop advanced technology solutions, including machine learning and network acceleration. Responsibilities include ASIC digital microarchitecture, RTL coding, design verification, and performance/power analysis for low-power hardware accelerators and SoCs. The role requires 6+ years of experience in hardware design engineering for production silicon and collaboration with cross-functional teams. Preferred qualifications include experience with infrastructure IP, subsystem integration, microcontroller clusters, and AI tools for workflow optimization and responsible AI practices.
Meta is seeking design engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.
Responsibilities
Minimum Qualifications
Preferred Qualifications
$146,000/year to $209,000/year + bonus + equity + benefits
Responsibilities
- Contribute to ASIC digital µArchitecture and design
- Assist in the performance/power analysis of the design and help meet power and performance targets
- Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration
- Collaborate with adjacent teams such as Verification, Physical Design, and Design for Test
- Develop micro-architecture, RTL coding, and design verification for complex IPs
- Drive the IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
- 6+ years of experience as a hardware design engineer for production silicon shipped in volume
- Experience in digital design µArchitecture, RTL coding, and micro-architecture development
- Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams
Preferred Qualifications
- Experience with one or more infrastructure IP areas, such as clock generation, distribution, and power management
- Exposure to subsystem-level implementation or integration, in any part of the flow from specification through RTL signoff
- Interest in growing into an infrastructure IP and subsystem implementation role
- Experience with microcontroller clusters
- Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
- Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
- Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
$146,000/year to $209,000/year + bonus + equity + benefits
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