Meta Verified
Social Media, Technology, Virtual Reality, Advertising
ASIC Engineer, Architecture Kernel Development
Sunnyvale, TXOnsiteFull Time$146,000–$209,000 /yrPosted 1 month agoVisa sponsorship available
Required skills
- ASIC
- kernel development
- AI/ML
- accelerators
- data centers
- performance analysis
- compiler
- ISA
- optimizations
- RTL simulation
Nice to have
- ML performance optimization
- compute kernels
- collective kernels
- SSE
- AVX
- NEON
Role summary
Meta is looking for an ASIC Engineer specializing in Architecture Kernel Development to join their infrastructure team. This role involves building accelerators for AI/ML workloads, enabling efficient data center scaling. You will work with AI/ML experts to architect machine learning accelerators, contribute to PyTorch backend prototyping, and develop "Green" data center accelerators. Responsibilities include developing AI kernels, creating performance analysis tools, debugging performance simulators, and validating performance on RTL simulation/emulation.
Meta is seeking an ASIC engineer, architecture kernel development to join our infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates, and upon which our innovative services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads, enabling our data centers to scale efficiently. You will have an opportunity to work with AI/ML experts in the company, help architect state-of-the-art machine learning accelerators and contribute to prototyping a reference PyTorch backend for these accelerators. Come work and learn alongside our engineers to build “Green” data center accelerators.
Responsibilities
Minimum Qualifications
Preferred Qualifications
$146,000/year to $209,000/year + bonus + equity + benefits
Responsibilities
- Work on developing AI kernels for Meta AI models on Meta AI Accelerators
- Develop tools for static performance analysis. Debug performance on the dynamic performance simulator
- Identify the compiler, ISA, and optimizations. Help validate performance on RTL simulation / emulation
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 6+ years of experience in software development mapping massively parallel workloads for HPC or kernel development
- Programming in C, C++, Python, or related programming languages
- Experience with computer architecture or tools for silicon development
Preferred Qualifications
- Master’s or PhD degree in Electrical Engineering, Computer Engineering or related areas with experience in driving ML performance optimization and trade-offs
- Experience in developing and optimizing compute or collective kernels using CUDA or similar programming models (SSE, AVX, NEON, Hexagon DSP, etc.)
- Understanding of GPU architectures or other AI accelerator architectures
- Experience working in pre-silicon validation processes, including development and validation with pre-silicon tools and models
- Experience with firmware development, API design, device driver development, and library implementation
$146,000/year to $209,000/year + bonus + equity + benefits
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