Meta Verified
Social Media, Technology, Virtual Reality, Advertising
DPU Power Architect, Infrastructure Silicon
Sunnyvale, TXOnsiteFull Time$178,000–$250,000 /yrPosted 1 month agoVisa sponsorship available
Required skills
- DPU
- Power Architect
- Infrastructure Silicon
- Data Processing Unit
- Power modeling
- Power analysis
- Power optimization
- Performance-per-watt
- Workload analysis
- System-level power models
Nice to have
- Power management firmware
- Software co-design
- On-die power telemetry
- Closed-loop power control
- Closed-loop thermal control
- Simulation environments
Role summary
Meta's Infrastructure Silicon team is seeking an experienced Power Architect to design and optimize Data Processing Units (DPUs). This role involves driving power modeling, analysis, and architectural optimization from early design stages through RTL and gate-level analysis. You will analyze DPU workloads, build system-level power models, quantify trade-offs for performance-per-watt, and define power-saving features. Responsibilities include owning power budgets, collaborating with cross-functional teams, and correlating pre-silicon projections with post-silicon measurements. Proficiency in Python, C/C++, and SystemC is required, with a strong understanding of SoC pipelines and data movement impacts on power.
Meta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We are seeking an experienced Power Architect to drive power modeling, analysis, and architectural power optimization of our Data Processing Unit (DPU) designs. In this role you will influence architecture and microarchitecture decisions from early path-finding through RTL/gate-level power analysis and silicon correlation, ensuring our DPUs deliver leading performance-per-watt on real data center workloads.
Responsibilities
Minimum Qualifications
Preferred Qualifications
$178,000/year to $250,000/year + bonus + equity + benefits
Responsibilities
- Analyze and characterize real-world DPU software use cases (network virtualization, storage offload, crypto/compression, packet processing) to identify hardware power bottlenecks and power-relevant behaviors
- Build and maintain workload-driven, system-level power models and power rollups for current and future SmartNIC/IPU/DPU architectures, tracking accuracy from early analytical estimates through RTL and gate-level power analysis
- Quantify architectural and micro-architectural trade-offs with respect to PPA, with emphasis on energy-per-transaction, power-per-bit moved, and performance-per-watt, to inform and guide design decisions
- Define and drive structural power-saving architecture features, including DVFS, AVS, power gating, clock gating, activity throttling, power state management, and workload-aware power policies
- Analyze SoC pipelines and data movement paths (host-to-DPU, memory/fabric/network traffic) to understand and optimize the power-versus-performance trade-off
- Own power budgets and provide power-delivery and thermal inputs in partnership with design, physical design, firmware, platform, and software teams
- Correlate pre-silicon power projections with post-silicon measurements and drive methodology improvements based on findings
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Experience in workload analysis and characterization, and abstracting power-relevant behaviors into models for architectural analysis
- Experience building system-level power models and power rollups, and tracking them from early estimates through RTL/gate-level power
- Experience defining or evaluating architectural power-saving features such as DVFS, power gating, and clock gating
- Understanding of SoC pipelines and how data movement impacts power versus performance
- Proficiency in programming languages for model development and automation (e.g., Python, C/C++, SystemC)
- Experience driving analysis independently and influencing architectural direction through data
Preferred Qualifications
- PhD in Computer Science, Computer Engineering or Electrical Engineering
- 15+ years of relevant industry experience in power architecture and power modeling for high-performance SoCs
- Experience with power management firmware/software co-design, on-die power telemetry, and closed-loop power/thermal control
- Experience with simulation/emulation environments used in ASIC development flows, including emulation-based activity capture (FSDB/SAIF) for long-window power analysis
- Experience with low-power implementation flows, including multi-voltage/UPF power intent, retention and isolation strategies
- Experience building or scaling power modeling and power regression infrastructure for hyperscale data center ASICs (network, storage, or AI accelerator designs)
- Familiarity with post-silicon power measurement, telemetry, and model-to-hardware correlation methodologies
- Experience with industry-standard power estimation and sign-off tools (e.g., Synopsys PrimePower/PTPX, Cadence Joules, Ansys PowerArtist) for power analysis and optimization
- Familiarity with power delivery network, voltage droop/di-dt analysis, and rack/platform-level power and thermal constraints
$178,000/year to $250,000/year + bonus + equity + benefits
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