ASIC Engineer, Implementation - Timing

Sunnyvale, TXOnsiteFull Time$114,000–$172,000 /yrPosted 1 month agoVisa sponsorship available

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Required skills

ASIC Implementation
Timing
Static Timing Analysis
Timing Closure
SDC
PrimeTime
Python
Tcl
Perl
Logic Synthesis

Nice to have

RTL Design
SystemVerilog
Advanced Process Nodes
On-Chip Variation
Multi-Corner Multi-Mode Analysis
Physical Design

Role summary

Meta's Infrastructure Silicon team is hiring an ASIC Implementation Engineer specializing in timing to design and deliver custom silicon for data centers. This role involves driving static timing analysis and timing closure for complex System on Chip designs, ensuring performance, power, and area targets are met at advanced process nodes. Responsibilities include developing timing constraints, performing analysis with industry-standard tools, collaborating with physical design engineers, and optimizing timing paths. The role also requires scripting for automation, interfacing with foundry teams, and supporting design handoffs. A Bachelor's degree and 2+ years of ASIC implementation experience focused on timing are required.

Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer specializing in timing to help design and deliver custom silicon for data center applications. In this role, you will drive static timing analysis and timing closure across complex System on Chip designs, working at the intersection of front-end and back-end implementation to ensure our infrastructure chips meet performance, power, and area targets at advanced process nodes.

Responsibilities

Develop and maintain timing constraints (SDC) for complex SoC designs, including clock definitions, input/output delays, multicycle paths, and false paths
Perform static timing analysis using industry-standard sign-off tools to identify and resolve setup, hold, and clock skew violations across hierarchical design blocks
Drive timing closure through collaboration with physical design engineers, providing guidance on placement, routing, and clock tree synthesis to meet timing targets
Analyze and debug timing paths across multiple clock domains, identifying critical paths and recommending RTL or physical implementation optimizations
Generate and validate timing reports for sign-off across process, voltage, and temperature corners, including on-chip variation analysis
Develop and maintain timing exception methodologies and waiver processes in coordination with design and verification teams
Contribute to the development and improvement of timing closure scripts and automation flows using scripting languages to increase efficiency and repeatability
Interface with foundry and library teams to characterize and integrate timing libraries, including standard cells, memories, and hard IP
Support design handoff between front-end and back-end teams by providing timing-aware synthesis netlists and constraint validation

Minimum Qualifications

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
Currently has a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2+ years of experience in ASIC implementation with a focus on static timing analysis and timing closure
Experience with industry-standard static timing analysis and sign-off tools such as PrimeTime or equivalent
Experience developing and validating SDC timing constraints for complex SoC or IP designs
Experience with logic synthesis tools and timing-driven optimization techniques
Experience scripting in Python, Tcl, or Perl to automate timing analysis and reporting flows

Preferred Qualifications

Experience with RTL design or synthesis using SystemVerilog or other hardware description languages
Experience with timing closure at advanced process nodes (7nm or below), including on-chip variation and multi-corner multi-mode analysis
Familiarity with physical design concepts such as placement, routing, and parasitic extraction as they relate to timing closure
Experience with clock tree synthesis and clock network optimization in the context of timing sign-off

$114,000/year to $172,000/year + bonus + equity + benefits

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ASIC Engineer, Implementation - Timing

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Required skills

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