
Space Electronics Engineer Level 2-3
Required skills
- EGSE
- Test Set Design Engineer
- Flight hardware
- ground test
- power
- control
- telemetry
- safety interlocking
- cooling
- panel design
Nice to have
- Electrical Engineering
- integrated hardware design
- analog
- digital
- lab test equipment
- DMM
Role summary
Job Title: Space Electronics Engineer Level 2-3. Summary unavailable (incomplete response).
Description
At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.We have an opening for an experienced Electronics Engineer to join our team of qualified, diverse individuals in the Space Systems organization. This position is in Baltimore, MD.
This requisition is for a Test Set Design Engineer, who will be responsible for the design and fabrication of the Electrical Ground Support Equipment (EGSE) suite of test sets. The EGSE test sets are used to checkout, integrate, and operate Flight hardware during ground test. These test sets provide power, control, telemetry, safety interlocking and cooling. This candidate will be part of a small EGSE Design Team supporting a few programs.
Responsibilities include but are not limited to:
- Panel & cable design, electrical interconnects & schematics, developing acceptance criteria & certification procedures, and hardware checkout/troubleshooting.
- Root cause determination, problem resolution and documentation is expected.
- Perform hands-on integration, checkout, and troubleshooting of test equipment builds in a lab environment including electrical/continuity checks and functional testing
- Interface with subsystem test engineers, test operators, technicians, systems administrators, security team, and vendors to provide support for various test set tasks as required.
- Full design cycle of EGSE, from conception through design to fabrication and integration/test.
Basic Qualifications:
- For Level 2: Bachelor's degree in a STEM discipline with 2 years of relevant experience; 0 years of relevant experience with a Master's degree
- For Level 3: Bachelor's degree in a STEM discipline with 5 years of relevant experience; 3 years of relevant experience with a Master's degree; 1 year of relevant experience with a PhD
- Proficient in hardware design to include panel and/or cable design, schematic layouts, etc.
- Minimum of 3 years’ experience in hardware design
- Active SECRET clearance, with the ability to obtain and maintain TS/SCI, is required
Preferred Qualifications:
- Advanced degree in Electrical Engineering or related STEM discipline
- Proficient with hands-on troubleshooting with electrical hardware
- Proficient with integrated (analog, power, digital) hardware design
- Proficient with lab test equipment, such as DMMs, O-Scopes, or related
- Proficient with electrical design tools (e.g., Zuken, AutoCAD, PSpice)
- Proficient in Test Automation Software (LabView, TCL, MatLab)
- Active or Current TS/SCI Clearance preferred
Sample Northrop Grumman interview questions
- 1
Can you discuss the role of reusability and scalability in UVM's verification approach?
technicalmedium - 2
Can you detail the function of a register table within embedded system design?
technicalmedium - 3
Could you outline how virtual memory is implemented in embedded systems and its advantages?
system designmedium - 4
Can you discuss the role and functionality of a watchdog timer?
system designmedium - 5
What is your understanding of polymorphism in SystemVerilog?
technicalmedium
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