
Principal/ Sr. Principal FPGA Design Engineer
Required skills
- FPGA
- ASIC
- VHDL
- Verilog
- High-level synthesis
- Xilinx Vivado HLS
- Mentor Catapult HLS
- C++
- Timing closure
- DSP structures
Nice to have
- Top Secret with SCI/SAP
- Digital Signal Processing algorithms
- Image Processing algorithms
- High-speed interfaces
- AXI
- PCIe
Role summary
Northrop Grumman Space Systems is seeking a Principal/Sr. Principal FPGA Design Engineer with signal processing experience to join their team in Rolling Meadows, IL. The role involves research, requirements analysis, systems architecture, design, coding, test bench design, verification, synthesis, and place & route for digital signal processing products. Responsibilities include working with digital subsystems and circuit card designs utilizing Xilinx, Intel (Altera), and Microsemi FPGAs, supporting high-speed interfaces, RF, EO DSP, controls, data links, embedded processing, and processor interfaces. Expertise in digital signal processing, modeling, simulation, and circuit-level design/test is desired. This position can be filled as a Level 3 or Level 4.
Description
At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.Embark on a career putting innovative, reliable, and agile products and ideas into orbit, and beyond. Northrop Grumman Space Systems has opportunities waiting for you that play a vital role in human space exploration, national defense, and scientific discovery, supporting multiple programs across the universe. With us, you’ll discover a culture of curiosity and collaboration that will have you Defining Possible from the day you start. Our space systems connect and protect millions of people on earth every day, now and for the future. Explore your future and launch your career with Northrop Grumman Space Systems today!
Our team is chartered with providing the skills, innovative technologies to develop, design, produce and sustain optimized product lines across the sector while providing a decisive advantage to the warfighter. Come be a part of our mission!
We are seeking a talented FPGA Design engineer with signal processing experience to join our growing team in Rolling Meadows, IL.
As an FPGA Design Engineer, you will join our diverse team and be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and place & route for our digital signal processing products. You will be working with digital subsystem and circuit card designs that utilize the latest FPGA technologies from all major vendors and device families including Xilinx, Intel (Altera), and Microsemi (Actel) and support high speed interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Your expertise in digital signal processing, modeling and simulation, and circuit level design and test are desired for this position.
This position will be filled as a level 3 or level 4.
Basic Qualifications
- Principal FPGA Design Engineer (Level 3): Bachelors’ degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 5 years (or MS and 3+ years, or a PhD) of FPGA/ASIC design experience.
- Sr. Principal FPGA Design Engineer (Level 4): Bachelors’ degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 8 years (or MS and 6+ years, or PhD +3 years) of FPGA/ASIC design experience.
- In-depth knowledge of VHDL and/or Verilog
- -Proficiency in High level synthesis (Xilinx Vivado HLS AND/OR Mentor Catapult HLS) with C++
- Expertise achieving timing closure on dense FPGA designs
- Working knowledge of DSP structures and techniques
- Proficient in Python, C or other scripting languages
- Extensive experience generating test benches
- Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis
- Experience with FPGA simulation tools to verify performance of complex RTL blocks
- Experience with Xilinx or Intel/Altera FPGA architectures and design tools
- Soft skills to include: Adaptive, creative, collaborative, comfortable working independently, enjoys solving difficult problems while communicating with all levels of an organization internally and externally
- Must be a US Citizen with ability to obtain and maintain Top Secret security clearance with SCI
Preferred Qualifications:
- Current or Active Top Secret with SCI/SAP security clearance
- Extensive experience implementing Digital Signal or Image Processing algorithms on FPGAs
- Extensive experience with high-speed interfaces: Ex. AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet, etc.
- Working knowledge of SDR platforms and architectures
- Extensive experience developing FPGA algorithms for SoC based architectures
- Experience developing FPGA/SW interfaces and controls
- Experience developing and prototyping in MATLAB/Simulink
- Experience debugging down to the hardware level & experience using Signal Generators, Logic Analyzers, Digital Oscilloscopes and Embedded FPGA
- Debugging tools.
- Experience and knowledge developing requirements for FPGA-based products
- Experience with Electronic Design Automation (EDA) Tools: Mentor Graphics ModelSim/QuestaSim, Synplify, Xilinx ISE/ Vivado, Intel Quartus, Altera SOPC Builder, Altera Qsys, DSP Builder.
- Experience working with or developing test benches using SystemVerilog and Universal Verification Methodology (UVM)
- -Familiarity with revision control, documentation, planning, and review systems similar to GIT/SVN/ClearCase, DOORS, Jira/Rally/ClearQuest
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Sample Northrop Grumman interview questions
- 1
Can you discuss the role of reusability and scalability in UVM's verification approach?
technicalmedium - 2
Can you detail the function of a register table within embedded system design?
technicalmedium - 3
Could you outline how virtual memory is implemented in embedded systems and its advantages?
system designmedium - 4
Can you discuss the role and functionality of a watchdog timer?
system designmedium - 5
What is your understanding of polymorphism in SystemVerilog?
technicalmedium
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