
SRAM/ROM Circuit Design Engineer
Required skills
- SRAM
- ROM
- memory compiler
- CMOS
- performance
- power
- area
- periphery circuits
- functional safety
- scan functionality
Nice to have
- advanced CMOS foundry technologies
- 5nm
- automotive design rules
- LLM
- GenAI
Role summary
NXP's Austin Memories team is seeking an experienced SRAM/ROM circuit design engineer to implement CMOS memory circuit designs, including periphery circuits for functional safety and scan. Responsibilities include generating and evaluating simulations, collaborating with layout and CAD teams for implementation, aligning with modeling/verification, and leveraging GenAI tools for efficiency. The role requires a Bachelor's degree in EE or related field, 8+ years of industry experience in SRAM design with advanced CMOS technologies, familiarity with Cadence Virtuoso and EDA tools, and knowledge of scripting languages like Python, Perl, or Tcl. Familiarity with automotive design rules and LLM/GenAI tools is a plus. This hybrid role is based in Austin, TX.
NXP’s Austin Memories team is seeking an experienced memory circuit design engineer for our SRAM and ROM internal memory compiler designs.
Our team is part of the Design Enablement/Foundation IP organization within the Chief Technology Office at NXP. We provide differentiating SRAM/ROM memory compiler solutions to NXP SoC design teams across multiple business lines- your work will have real impact for our design teams and, through them, our end products and end customers.
Job Summary:
Implement design of CMOS memory circuits to meet memory compiler performance, power, and area requirements, including periphery circuits to support functional safety and scan functionality.
Generate, execute, and evaluate simulation characterization measurements and simulation test benches, and compare vs. performance targets/benchmarks.
Engage with layout teams on implementation of compiler leaf cells based on designs to improve area and performance.
Work closely with CAD teams on implementation of new designs into our characterization, verification, and regression flows.
Align with modeling/verification team to ensure consistency of designs with frontend models (behavioral/ATPG/emulation).
Collaborate effectively across global memory teams to help ensure common methodologies and best practices.
Leverage internally supported LLM/GenAI tools and EDA vendor GenAI solutions to implement efficiencies in design methodologies.
Job Qualifications:
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline. (Master’s degree is preferred).
8+ years of industry experience (6+ with Master’s degree) in SRAM memory circuit design, including some design experience with advanced CMOS foundry technologies at 5nm and beyond.
Strong familiarity with Cadence Virtuoso and other industry-standard EDA tools.
Familiarity with automotive design rules and memory design requirements is a plus.
Good knowledge of scripting languages such as Perl, tcl, or Python is a must.
Creative mindset, with strong analytical and problem-solving skills.
Job location:
The position will be based at the NXP offices in Austin, Texas. Team members are expected to work in office at least 3 days/week.
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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