Design Verification Engineer, New Grad
Required skills
- SystemVerilog
- UVM
- testbenches
- tests
- checkers
- functional coverage
- regressions
- debug simulation failures
- RTL designers
- tape-out
Nice to have
- M.S
- internship
- AI tools
- Claude
Role summary
SambaNova Systems is seeking a new grad Design Verification Engineer to join their RDU chip verification team. This role involves writing testbenches, tests, checkers, and coverage in SystemVerilog and UVM for chip-level control and initialization features. Responsibilities include running regressions, debugging simulation failures, analyzing coverage, and collaborating with RTL designers to identify and resolve bugs before tape-out. A BS in a relevant engineering field and coursework/project experience in digital design and computer architecture are required, along with experience in SystemVerilog or Verilog, scripting languages (Python, Perl, TCL, shell), and UVM. Familiarity with constrained-random verification, functional coverage, assertions, and clock domain crossing concepts is also needed.
SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.
About the Team
The Design Verification team verifies the RDU, SambaNova's chip for AI workloads. We build SystemVerilog and UVM environments for chip-level control and initialization, including sequencing, state transitions, clocking, and recovery, and work with architects, RTL designers, and firmware engineers.
About the Role
As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out.
Responsibilities
Required Qualifications
Preferred Qualifications
Base Salary Range:
Base Pay Range$120,000—$150,000 USDSubmission GuidelinesPlease note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.
EEO PolicySambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.
Benefits Summary for US-Based, Full-Time Employment PositionsSambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.
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