Analog Design, Architect

Descriptions & Requirements

Job Description and Requirements We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent more than a decade making memory interfaces work in silicon, not just in simulation. You know the difference between a PHY that measures well on paper and one that actually survives customer bring-up at 4am with signal integrity issues no one predicted. When a test chip comes back and the eye diagram looks nothing like the model, you are the person who figures out why, and you do it methodically, without drama.You think about layout like it is part of the circuit, because you have seen too many designs fail because someone treated it as an afterthought. Power delivery, ground bounce, coupling, these are not abstract concepts to you. They are the reasons you ask specific questions during floorplan reviews and push back when something does not add up.You have debugged enough silicon to know that the best architecture decisions happen early, when you still have room to optimize for power, performance, and area without heroics later. You mentor without gatekeeping. You collaborate across time zones without losing clarity. At Synopsys, you will work on HBM interfaces that power the AI systems being built right now, and the team you join is global, technical, and expects you to lead.What You'll Be Doing

• Drive silicon-to-simulation correlation for HBM PHY test chips, identifying root causes when measured results diverge from models and feeding findings back into design methodology
• Support customer silicon bring-up and debug, working directly with engineering teams to diagnose signal integrity, power integrity, and functional issues in real deployment scenarios
• Define architecture for next-generation HBM PHY products, making tradeoffs across power, performance, and area that hold up in silicon, not just spreadsheets
• Design and validate analog and mixed-signal circuit blocks for high-speed memory interfaces, including PLLs, DLLs, drivers, receivers, and voltage regulators
• Collaborate with layout engineers to ensure circuit performance is preserved through physical implementation, reviewing and guiding floorplan, routing, and parasitic extraction
• Work with a cross-functional, multi-site team including digital designers, verification engineers, and product architects to deliver integrated PHY IP on aggressive schedules
• Mentor mid-level and junior analog designers, reviewing schematics, sharing debug techniques, and building design knowledge across the team

The Impact You Will Have

• Your architecture decisions will define the power and performance profile of HBM interfaces used in AI training and inference systems shipping in the next two years
• Your silicon correlation work will tighten the gap between simulation and reality, reducing respins and increasing first-pass success rates across the product line
• Your customer debug support will directly unblock production schedules for companies building next-generation data center and AI hardware
• Your circuit designs will be integrated into IP that ships in millions of devices, powering memory bandwidth at the edge of what is physically possible today
• Your layout-aware design approach will reduce late-stage surprises and improve yield, saving months of schedule and significant engineering cost
• Your mentorship will raise the technical bar for the entire analog design team, building institutional knowledge that outlasts any single project
• Your collaboration across a global team will help Synopsys maintain its position as a leading provider of high-speed interface IP in a market with no room for second place

What You'll Need

• MS or PhD in Electrical Engineering, with a focus on analog, mixed-signal, or RF circuit design
• 12+ years of hands-on experience designing analog and mixed-signal circuits for memory interfaces or high-speed die-to-die links
• Proven track record debugging silicon for memory interfaces, including root cause analysis of signal integrity, power integrity, and functional failures
• Deep understanding of how layout parasitics, substrate coupling, and power delivery affect circuit performance, with experience reviewing and guiding physical implementation
• Strong grounding in signal integrity and power integrity concepts, including transmission line effects, termination schemes, crosstalk, and simultaneous switching noise
• Experience defining or contributing to PHY architecture, making tradeoffs across power, performance, area, and complexity that survive contact with real customer requirements
• Scripting experience in Python, Perl, or similar for design automation, analysis, or post-processing is a strong plus, especially if you have explored AI-assisted design flows

Who You Are

• You can look at a silicon measurement that does not match simulation and form a hypothesis in minutes, not days, because you have seen this movie before and know where to look first
• You review a layout and immediately spot the ground return path that is going to cause problems, or the coupling that no one else flagged, because you think in 3D and understand parasitics are not optional
• You explain a complex PPA tradeoff to a product manager or customer in two sentences without losing the nuance, and you do it in a way that helps them make the right call
• You do not wait for perfect data to make a decision, you work with what you have, document your assumptions, and move forward with enough confidence to keep the team unblocked
• You mentor by showing, not telling, walking a junior engineer through a debug session or schematic review in a way that builds their skill, not just fixes the immediate problem
• You stay current on where the technology is going, whether that is new process nodes, new memory standards, or new design automation techniques, because standing still is not an option in this space

The Team You'll Be Part OfYou will join the High Bandwidth Memory (HBM) interface design team, a cross-functional, multi-site group of analog and mixed-signal designers working on next-generation memory PHY IP. The team collaborates globally with digital design, verification, product architecture, and customer engineering teams to deliver best-in-class IP for AI and high-performance computing applications. Your recruiter will share more about the team structure, current projects, and reporting relationships during the interview process.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

General Information

Job Title Analog Design, Architect Job ID 19529 City Boxborough State/Province Massachusetts Date Posted 28-Oct-2026 Job Category Engineering Job Subcategory Analog Design Hire Type Employee Remote Eligible No Base Salary Range: $200000 - $300000