Low-Power Design Engineer
Required skills
- low-power design
- UPF
- power-aware verification
- VC LP
- Conformal Low Power
- PowerArtist
- CDC
- RDC
- SpyGlass
- Questa CDC
Nice to have
- mobile power management
- edge power management
- data-center power management
- formal verification
- AI-assisted design
Role summary
Voltai is developing AI for semiconductor design, focusing on world models and agents to interact with the physical world. They are seeking a Low-Power Design Engineer with 5+ years of experience to own power intent from architecture through signoff. The role involves designing and verifying low-power architectures on real silicon programs, defining UPF power intent, implementing power gating and other low-power techniques, running power-aware simulations and checks, and collaborating with cross-functional teams. Experience with specific tools like VC LP, Conformal Low Power, PowerArtist, and CDC/RDC tools is required, along with Python or Tcl scripting skills. Bonus points for experience in mobile, edge, or data-center power management, formal verification, or interest in AI-assisted design.
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
About this Role
You'll own power intent from architecture through signoff. You'll design and verify low-power architectures on real silicon programs with leading semiconductor companies while helping Voltai's AI learn power-aware design.
What You’ll Do
Define power architecture and write UPF power intent for SoCs and IP.
Implement and verify power gating, clock gating, multi-voltage domains, and retention.
Run power-aware simulation, static low-power checks, and CDC/RDC analysis.
Partner with RTL, physical design, and signoff teams on power estimation and closure.
Build automation for power analysis and reporting.
Evaluate AI-generated power intent and help define what correct looks like.
What We’re Looking For
5+ years of low-power design or verification experience on production tapeouts.
Expert UPF knowledge and experience with power-aware verification.
Hands-on experience with tools like VC LP, Conformal Low Power, or PowerArtist.
Experience with CDC/RDC tools (SpyGlass, Questa CDC, or similar).
Python or Tcl scripting.
Bonus Points
Experience with mobile, edge, or data-center power management.
Formal verification of power intent.
Interest in AI-assisted design tools.
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