Layout/Mask Designer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Design complex custom layout for digital circuits in deep SubMicron CMOS technologies. Review and analyze floorplans and complex circuits with circuit designers. Run a complete set of layout design verification tools available on megacells . Work with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. Interpret LVS, DRC and ERC report to find the fastest way to complete layouts. Utilize advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Utilize advanced layout techniques to come up with best-in-class PPA for critical designs. Perform EMIR simulations and apply necessary fixes to achieve robust power delivery. Review the layouts designed by peers and provide improvement recommendations. Utilize automated P&R tools to speed up the layout execution of digital designs. 40 hours/week.

Minimum Qualifications

Bachelor's degree and foreign equivalent in electrical engineering or a related field and five (5) years of progressive, post-baccalaureate experience in the job offered or a related occupation. 5 years of experience with each of the following skills is required: Layout floor-planning, standard cell planning and hierarchical layout assembly. Understanding of issues with RC delay, electromigration, self-heating and cross capacitance. Recognizing failure prone layout structures, dedicatedly working with designers for the best approach to problems. Designing and validating a robust PG grid using IR simulations tools. Collaborating and communicating effectively with multi-functional teams. Interpreting CALIBRE DRC, ERC, LVS reports. Using CADENCE virtuoso layout design tools. Designing low noise, low power data-path or Memory layout structures.

Preferred Qualifications

N/A