
Layout/Mask Designer
Required skills
- Deep SubMicron CMOS
- layout floor-planning
- standard cell planning
- hierarchical layout assembly
- PPA
- RC delay
- electromigration
- self-heating
- cross capacitance
- failure prone layout structures
Role summary
Apple Inc. is seeking a Layout/Mask Designer in Austin, Texas, to design complex custom layouts for digital circuits in deep SubMicron CMOS technologies. The role involves working with layout leads and circuit designers to analyze floorplans, run verification tools, and resolve issues related to RC delay, electromigration, and self-heating. Responsibilities include interpreting LVS, DRC, and ERC reports, utilizing advanced CAD tools and mask design knowledge for corrections, and applying advanced layout techniques for optimal PPA. The designer will also review EMIR simulations and use automated P&R tools to enhance layout execution. This is a full-time, onsite position requiring 40 hours/week.
Description
APPLE INC has the following available in Austin, Texas. Design complex custom layout for digital circuits in deep SubMicron CMOS technologies. Work with Layout lead and circuit designers to review and analyze floorplans of complex circuits. Responsible to run a complete set of layout design verification tools available and clean up megacells to match engineering specifications. Work with Layout lead and circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. Interpret LVS, DRC and ERC report to find the fastest way to complete layouts. Utilize advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Utilize advanced layout techniques to come up with best-in-class PPA for critical designs. Work with design lead to review EMIR simulations and apply necessary fixes to achieve robust power delivery. Utilize automated P&R tools to speed up the layout execution of digital designs. 40 hours/week.
Minimum Qualifications
Bachelor’s degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation. 2 years of experience with each of the following skills is required: Using layout floor-planning, standard cell planning and hierarchical layout assembly to generate best PPA (power, performance and area) layouts Resolving issues with RC delay, electromigration, self-heating and cross capacitance. Recognizing failure prone layout structures, working with designers for the best approach to problems like shielding critical signals, analyzing DFM yields and LOD effects. Creating layouts with a robust PG grid using IR simulations tools Collaborating and communicating effectively with multi-functional teams to understand engineering spec and have on-time deliverables Interpreting CALIBRE DRC, ERC, LVS, and DFM reports to finish layout(s) Using CADENCE virtuoso layout design tools to draw layouts and increased productivity
Preferred Qualifications
N/A
Sample Apple interview questions
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