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Celero Communications Verified
Financial Technology (FinTech)

Principal DFT Engineer

Irvine, CAOnsiteFull TimePrincipal$200,000–$240,000 /yrPosted 1 month ago

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Required skills

  • ASIC
  • SoC
  • DFT
  • Scan Insertion
  • Scan Chain Planning
  • Scan Compression
  • ATPG
  • Fault Models
  • Test Coverage
  • MBIST

Nice to have

  • Compression architectures
  • Silicon validation
  • Manufacturing production ramps
  • Timing closure
  • Physical design impacts
  • Low-power design techniques

Role summary

Celero Communications is seeking a Principal DFT Engineer to join their silicon engineering team. This role involves developing and implementing Design-for-Test methodologies for complex ASIC and SoC products. Responsibilities include scan insertion, ATPG pattern generation, MBIST implementation, JTAG support, and DFT signoff. The ideal candidate will have 8+ years of ASIC/SoC DFT experience, strong understanding of test methodologies, and proficiency with relevant tools and scripting languages. Collaboration with cross-functional teams and participation in silicon bring-up and yield improvement are key aspects of this position.

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products.

What You Will Do

  • Develop and implement DFT architecture for ASIC and SoC designs.
  • Perform scan insertion, scan chain planning, and scan compression implementation.
  • Generate and validate ATPG patterns and analyze fault coverage results.
  • Implement and verify MBIST, and other on-chip test features.
  • Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
  • Support JTAG and boundary-scan implementation and debug.
  • Drive DFT signoff activities and manufacturing test readiness.
  • Participate in silicon bring-up, failure analysis, and yield improvement efforts.

    • What You Will Bring

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 8+ years of ASIC/SoC DFT experience.
  • Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
  • Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
  • Knowledge of Verilog/SystemVerilog and digital design fundamentals.
  • Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
  • Results-driven engineer with strong debugging abilities.
  • Comfortable working in fast-paced cross-functional environments.
  • Passion for delivering high-quality silicon products.

    • Preferred Qualifications

  • Experience with advanced-node semiconductor technologies.
  • Hands-on experience with MBIST, compression architectures, and JTAG.
  • Knowledge of timing closure, physical design impacts, and low-power design techniques.
  • Experience supporting silicon validation and manufacturing production ramps.
  • Strong communication and cross-functional collaboration skills.Annual Base Salary Range for US: $200,000 - $240,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
    • Ready to apply?
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