Lead DFT Engineer
Required skills
- DFT
- SoCs
- Hierarchical DFT
- Scan compression
- Boundary Scan
- MBIST
- scan insertion
- ATPG
- Stuck-at
- Transition
Nice to have
- edge deployment
- data center chips
- test coverage
- area overhead
- power impact
- timing analysis
Role summary
EnCharge AI is seeking a Lead DFT Engineer to architect and implement the end-to-end DFT strategy for complex SoCs used in advanced AI hardware for edge-to-cloud computing. This role involves defining strategies for Hierarchical DFT, Scan compression, Boundary Scan, MBIST, IST, and POST, ensuring manufacturability and reliability in power-constrained edge environments. Responsibilities include overseeing scan insertion, ATPG, memory/logic BIST, collaborating with cross-functional teams, and leading post-silicon validation on ATE. The ideal candidate will have 12+ years of DFT experience, including leadership, with expertise in industry-standard tools and advanced FinFET nodes.
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Lead DFT Engineer
Job Description:
Developing silicon for edge-to-cloud computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.
As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.
Key Responsibilities:
Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.
Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.
Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.
Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.
Technical Requirements:
Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Bachelor’s degree in a related field.
Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus).
Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).
Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).
Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.
EnCharge AI is an equal employment opportunity employer in the United States.
The salary range for this position is $200,000 to $250,000 USD/CAN per year. Actual compensation offered will be determined based on job-related knowledge, skills, and experience.
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