Physical Design Engineer
Required skills
- Synthesis
- PNR
- STA
- EM/IR
- LEC
- physical verification
- Genus
- Innovus
- Tempus
- Quantus
Nice to have
- low-power design
- sub-7nm node technologies
- TCL scripting
- Cadence
- Synopsys
Role summary
Seeking a Physical Design Engineer to execute synthesis, place and route (PNR), and static timing analysis (STA) for ASIC chip partitions. Responsibilities include collaborating with architects and RTL designers, resolving implementation issues, closing EM/IR, driving LEC and physical verification signoff, and contributing to methodology refinement. Requires 7+ years of experience in physical design, proficiency with EDA tools like Genus and Innovus, and a strong understanding of physical design flows. Preferred qualifications include experience with low-power design, sub-7nm nodes, SoC design, and TCL scripting.
Physical Design Engineer
San Jose ,CA
Job Responsibilities:
Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.
Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Genus ,Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
Genus ,Innovus are must have
Preferred Qualifications
7+ years of experience in physical design roles and related activities.
Proven ability to adhere to tight schedules and implement low-power design techniques.
Experience in System-on-Chip (SoC) design and implementation.
Expertise in sub-7nm node technologies.
Familiarity with industry-standard EDA tools and their capabilities.
Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.
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