Technical Program Manager

Boston, MAHybridFull TimePosted 11 days ago

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Required skills

semiconductor
hardware development
program manager
technical program manager
wafer-scale photonic systems
packaging
assembly
silicon
system bring-up
schedule

Nice to have

advanced packaging
2.5D/3D
chiplet
flip chip
multi-die packages
mechanical stress

Role summary

Seeking a Technical Program Manager to own programs for wafer-scale photonic systems, working closely with engineering teams from packaging to system bring-up. This hands-on role requires ownership of schedules, risks, and inter-team handoffs, with a focus on driving tasks to completion. Ideal candidates have 8+ years in semiconductor or hardware development, with deep knowledge in advanced packaging or ASIC/SoC and system hardware. Experience managing external partners is essential. Preferred qualifications include expertise in advanced packaging techniques, chip-on-wafer assembly, photonic systems, reliability, and ASIC tape-outs.

What We're Looking For

We're looking for technical program managers to own programs across our wafer-scale photonic systems. Each TPM owns one program and works embedded with the engineering team that carries most of it, from packaging and assembly to silicon and system bring-up. We have two openings.
This is a hands-on role. You'll own the schedule, the risks and the handoffs between teams, and you'll work in the technical details alongside the engineers. We want someone who gets things done themselves, not someone who only tracks status.

Ideal Background

8+ years in semiconductor or hardware development, as an engineer, a program manager or both, with programs taken from development to working hardware
Deep working knowledge of at least one of: advanced packaging and assembly, or ASIC/SoC and system hardware
Communicates clearly and directly with engineers, partners and leadership
Reads specifications closely and spots gaps, conflicts and missing owners
Action-oriented — builds plans and schedules that engineers actually use, and drives them to done
Experience running work with external partners (foundries, OSATs, IP or design-services vendors)

Nice to Have

Advanced packaging (2.5D/3D, chiplet, flip chip), including complex multi-die packages
Experience with chip-on-wafer (CoW) assembly, including mechanical stress and thermal effects
Photonic, optoelectronic or other heterogeneous-material assemblies
Reliability qualification, failure analysis, test vehicles and DOEs
Advanced-node ASIC/SoC tape-outs and work with third-party IP or design-services partners
Multi-die, chiplet or MCM programs, including chip-package co-design
System hardware (boards, power, thermal, mechanical) through bring-up
Optical I/O or high-speed SerDes programs
Data-center or OCP-style hardware
Experience with Jira and Confluence

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