Physical Design Engineer
Required skills
- physical design
- netlist
- GDSII
- floorplanning
- placement
- clock tree synthesis
- routing
- timing closure
- synthesis
- STA
Nice to have
- full-chip integration
- hierarchical design
- high-speed design
- low-power design
- AI
- machine learning
Role summary
Voltai is developing AI to design and create hardware, electronics, and semiconductors. They are seeking a Physical Design Engineer to take designs from netlist to GDSII, owning floorplanning through closure on real silicon programs. The role involves driving timing, power, and congestion closure, physical verification, and improving place-and-route flows. You will also evaluate AI-generated designs and work with customer teams. This role requires 5+ years of experience with multiple production tapeouts, deep experience with specific EDA tools, advanced node experience, and strong scripting skills.
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
About this Role
You'll take designs from netlist to GDSII. You'll own floorplanning through closure on real silicon programs with leading semiconductor companies while helping Voltai's AI learn how expert physical designers make decisions.
What You’ll Do
Own block-level and full-chip physical implementation: floorplanning, placement, clock tree synthesis, and routing.
Drive timing, power, and congestion closure with synthesis and STA teams.
Close physical verification (DRC/LVS) and power integrity (IR drop, EM) for signoff.
Build and improve place-and-route flows and automation.
Evaluate AI-generated floorplans and implementation decisions, and help define what good looks like.
Work directly with customer teams on implementation challenges.
What We’re Looking For
5+ years of physical design experience with multiple production tapeouts.
Deep experience with Innovus or Fusion Compiler/ICC2.
Strong understanding of timing closure, clock tree synthesis, and power distribution networks.
Experience at advanced nodes (7nm and below).
Strong Tcl and Python scripting.
Bonus Points
Full-chip integration or hierarchical design experience.
Experience with high-speed or low-power designs.
Interest in AI or machine learning applied to physical design.
Similar roles
- Emulation & FPGA Prototyping EngineerVoltai · Palo Alto, CA
- Low-Power Design EngineerVoltai · Palo Alto, CA
Physical Design EngineerBroadcom · San Jose, CA · Onsite
Physical Design EngineerAMD · Markham, ON · Hybrid- Sr. Staff / Principal Physical Design EngineerSK hynix memory solutions America Inc. · San Jose, CA · Onsite
Principal Physical Design Engineer / Physical Design – ACE USNXP Semiconductors · Austin, TX · Onsite
